The present invention relates to a semiconductor Integrated circuit device and, more particularly, to a technique which may be effectively applied to a semiconductor integrated circuit device having bipolar transistors and MISFETs provided on the same substrate.
Japanese Patent Application No. 59-225738 (1984) discloses one type of bipolar transistor which is called an SICOS (Side Wall Base Contact Structure) bipolar transistor. In this transistor, the base electrode is self-alignedly connected to the base region, and the emitter region is self-alignedly formed with respect to the base electrode and the base region. For this reason, it is possible to produce a small transistor and achieve an increase in the operation speed of the device.
The present inventors studied an integrated circuit formed using bipolar transistors of the type described above.
The above-described type of bipolar transistor is superior in both the operation speed and driving capability but inferior to MISFETs in terms of capability in reducing the size of the device. Accordingly, the present inventors contrived to use the above-described SICOS bipolar transistors to constitute a portion of an integrated circuit which is regarded as requiring high-speed operation capability and high driving capability and employ MISFETs to constitute a portion of the circuit in which miniaturization is regarded as important.